1. Field of the Invention
This invention relates to integrated circuit decoupling capacitors. More specifically, a decoupling capacitor stack that can be inserted between the top metal layer and a bump metal layer in the back end chip interconnection.
2. Background
The operation of low power, high speed integrated circuits can be affected by the electrical noise generated by the continuous switching of the transistors located in the circuit. It is well known that the inductive noise of an integrated circuit can be reduced by connecting decoupling capacitors to the circuit. Decoupling capacitors placed on power-consuming circuits are able to smooth out voltage variations with the stored charge on the decoupling capacitor. The stored charge is used as a local power supply to device inputs during signal switching stages, allowing the decoupling capacitor to mitigate the effects of voltage noise induced into the system by parasitic inductance.
Typically, a decoupling capacitor is placed in the same package as the chip. Unfortunately, this arrangement is costly to manufacturer, and the long lead lines from the power-consuming circuit to the capacitor electrodes contributes a substantial inductance. Such off-chip decoupling capacitors, however, are not sufficient for very high speed microprocessor applications. The voltage drop across an inductor is L di/dt, where L is inductance and di/dt represents the change in current through a circuit over a period of time. Implicit in the di/dt is a frequency term omega, so as frequency goes up, inductance becomes more and more a factor for power distribution. The frequency dependent Ldi/dt voltage drop makes the off-chip capacitors unusable with gigahertz switching circuits unlike low frequencies for which voltage drops are dominated by resistance.
Some efforts have been made to integrate decoupling capacitors as part of the gate dielectric processing step. A portion of the active silicon area is used to deposit the gate dielectric for use as a decoupling capacitor. An advantage to this is that there are no additional processing steps involved with it. The disadvantages include this decoupling capacitor takes up high-value real estate on the chip as the capacitors compete for valuable die area that could be used for building additional circuits. Also the capacitor made with a gate oxide designed for very high transistor performance has a great deal of leakage. These gate decoupling capacitors also have associated parasitic resistance from the relatively low Si conductivity which entail an additional RC time constant for charge extraction. Although it is possible to integrate gate capacitors within the chip""s circuit elements, due to the limited area in which to build these capacitors, the overall capacitive decoupling that they provide is also limited.
Another approach to decoupling capacitor fabrication is a decoupling capacitor that may be fabricated between the metal 6 (n-1) layer and the metal layer 7 (n) in an integrated circuit. The advantage to this embodiment is there is no additional real estate on the chip taken up for fabrication of the decoupling capacitor, and the decoupling capacitor directly bridges the on-die power grid being between 0 and 10 microns from the integrated circuit element it is supporting with a very low inductance per unit length due to the tight spacing of the power and ground lines. An off-chip decoupling capacitors are typically over a millimeter in distance from the circuit element it is supporting with a larger power to ground separation, with higher inductance per unit length. One problem with this technique is that only approximately 30 percent of the metal 6 layer is devoted to power supply. This limits the total amount of decoupling capacitance that can be provided on-die per layer.